

module B_type(
    input [2:0] funct3,
    input [31:0] iaddr,
    input signed [31:0] imm,
    input signed [31:0] in1,
    input signed [31:0] in2,
    output reg [31:0] out,
    output reg jump_flag
);

    wire [31:0] tmp1, tmp2;  //autochip reg
    assign tmp1 = in1;
    assign tmp2 = in2;

    always @(*) begin
        
        //jump_flag = 0; 

        case(funct3)
		3'b000:   //autochip���ɵĶ�û��begin end
		  begin
		  out = (in1==in2)? (imm-12) : (0);	//(imm-12)
		  jump_flag = (in1==in2)?1:0;
		  end
		3'b001: 
		  begin
		  out = (in1!=in2)? (imm-12) : (0);
		  jump_flag = (in1!=in2)?1:0;
		  end
        3'b100: 
		  begin
		  out = (in1<in2)? (imm-12) : (0);
		  jump_flag = (in1<in2)?1:0;
		  end
        3'b101: 
		  begin
		  out = (in1>=in2)? (imm-12) : (0);
		  jump_flag = (in1>=in2)?1:0;
		  end
        3'b110: 
		  begin
		  out = (tmp1<tmp2)? (imm-12) : (0);
		  jump_flag = (tmp1<tmp2)?1:0;
		  end
        3'b111: 
		  begin
		  out = (tmp1>=tmp2)? (imm-12) : (0);
		  jump_flag = (tmp1>=tmp2)?1:0;
		  end
            
        default: begin 
	    jump_flag = 0; 
	    out = 32'd0; 
	    end
        endcase
    end
endmodule

